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<title>PSHUFD—Shuffle Packed Doublewords </title></head>
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<h1>PSHUFD—Shuffle Packed Doublewords</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F 70 /<em>r</em> ib</p>
<p>PSHUFD <em>xmm1</em>, <em>xmm2/m128</em>, <em>imm8</em></p></td>
<td>RMI</td>
<td>V/V</td>
<td> SSE2</td>
<td>Shuffle the doublewords in <em>xmm2/m128</em> based on the encoding in <em>imm8</em> and store the result in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.128.66.0F.WIG 70 /r ib</p>
<p>VPSHUFD <em>xmm1, xmm2/m128, imm8</em></p></td>
<td>RMI</td>
<td>V/V</td>
<td>AVX</td>
<td>Shuffle the doublewords in <em>xmm2/m128</em> based on the encoding in <em>imm8</em> and store the result in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.256.66.0F.WIG 70 /r ib</p>
<p>VPSHUFD <em>ymm1, ymm2/m256, imm8</em></p></td>
<td>RMI</td>
<td>V/V</td>
<td>AVX2</td>
<td>Shuffle the doublewords in <em>ymm2/m256 </em>based on the encoding in <em>imm8</em> and store the result in <em>ymm1</em>.</td></tr>
<tr>
<td>
<p>EVEX.128.66.0F.W0 70 /r ib</p>
<p>VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle the doublewords in xmm2/m128/m32bcst based on the encoding in imm8 and store the result in xmm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F.W0 70 /r ib</p>
<p>VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle the doublewords in ymm2/m256/m32bcst based on the encoding in imm8 and store the result in ymm1 using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F.W0 70 /r ib</p>
<p>VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle the doublewords in zmm2/m512/m32bcst based on the encoding in imm8 and store the result in zmm1 using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RMI</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>imm8</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Copies doublewords from source operand (second operand) and inserts them in the destination operand (first operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the 256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high 128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand (see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of the source operand will be copied to doubleword 0 of the destination operand.</p>
<p>For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p>
<p>SRC</p>
<p>X7</p>
<p>X6</p>
<p>X5</p>
<p>X4</p>
<p>X3</p>
<p>X2</p>
<p>X1</p>
<p>X0</p>
<p>DEST</p>
<p>Y7</p>
<p>Y6</p>
<p>Y5</p>
<p>Y4</p>
<p>Y3</p>
<p>Y2</p>
<p>Y1</p>
<p>Y0</p>
<p>00B - X4</p>
<p>Encoding</p>
<p>00B - X0</p>
<p>Encoding</p>
<p>01B - X5</p>
<p>of Fields in</p>
<p>ORDER</p>
<p>01B - X1</p>
<p>of Fields in</p>
<p>10B - X6</p>
<p>ORDER</p>
<p>10B - X2</p>
<p>ORDER</p>
<p>11B - X7</p>
<p>Operand</p>
<p>7</p>
<p>56</p>
<p>4</p>
<p>3</p>
<p>12</p>
<p>0</p>
<p>11B - X3</p>
<p>Operand</p>
<h3>Figure 4-16.  256-bit VPSHUFD Instruction Operation</h3>
<p>The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword location in the destination operand.</p>
<p>In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.</p>
<p>128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-tion operand is an XMM register. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.</p>
<p>VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-tion operand is an YMM register. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed. Bits (255-1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the imme-diate byte as the order operand.</p>
<p>EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-tion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.</p>
<p>Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using the immediate byte as the order operand.</p>
<p>Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<h2>Operation</h2>
<p><strong>PSHUFD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[31:0] (cid:197) (SRC &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] (cid:197) (SRC &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] (cid:197) (SRC &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] (cid:197) (SRC &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VPSHUFD (VEX.128 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) (SRC &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] (cid:197) (SRC &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] (cid:197) (SRC &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] (cid:197) (SRC &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VPSHUFD (VEX.256 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) (SRC[127:0] &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[63:32] (cid:197) (SRC[127:0] &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[95:64] (cid:197) (SRC[127:0] &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[127:96] (cid:197) (SRC[127:0] &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[159:128] (cid:197) (SRC[255:128] &gt;&gt; (ORDER[1:0] * 32))[31:0];
DEST[191:160] (cid:197) (SRC[255:128] &gt;&gt; (ORDER[3:2] * 32))[31:0];
DEST[223:192] (cid:197) (SRC[255:128] &gt;&gt; (ORDER[5:4] * 32))[31:0];
DEST[255:224] (cid:197) (SRC[255:128] &gt;&gt; (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:256] (cid:197) 0</pre>
<p><strong>VPSHUFD (EVEX encoded versions)</strong></p>
<pre>(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF (EVEX.b = 1) AND (SRC *is memory*)
         THEN TMP_SRC[i+31:i] (cid:197) SRC[31:0]
         ELSE TMP_SRC[i+31:i] (cid:197) SRC[i+31:i]
    FI;
ENDFOR;
IF VL &gt;= 128
    TMP_DEST[31:0] (cid:197) (TMP_SRC[127:0] &gt;&gt; (ORDER[1:0] * 32))[31:0];
    TMP_DEST[63:32] (cid:197) (TMP_SRC[127:0] &gt;&gt; (ORDER[3:2] * 32))[31:0];
    TMP_DEST[95:64] (cid:197) (TMP_SRC[127:0] &gt;&gt; (ORDER[5:4] * 32))[31:0];
    TMP_DEST[127:96] (cid:197) (TMP_SRC[127:0] &gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
IF VL &gt;= 256
    TMP_DEST[159:128] (cid:197) (TMP_SRC[255:128] &gt;&gt; (ORDER[1:0] * 32))[31:0];
    TMP_DEST[191:160] (cid:197) (TMP_SRC[255:128] &gt;&gt; (ORDER[3:2] * 32))[31:0];
    TMP_DEST[223:192] (cid:197) (TMP_SRC[255:128] &gt;&gt; (ORDER[5:4] * 32))[31:0];
    TMP_DEST[255:224] (cid:197) (TMP_SRC[255:128] &gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
IF VL &gt;= 512
    TMP_DEST[287:256] (cid:197) (TMP_SRC[383:256] &gt;&gt; (ORDER[1:0] * 32))[31:0];
    TMP_DEST[319:288] (cid:197) (TMP_SRC[383:256] &gt;&gt; (ORDER[3:2] * 32))[31:0];
    TMP_DEST[351:320] (cid:197) (TMP_SRC[383:256] &gt;&gt; (ORDER[5:4] * 32))[31:0];
    TMP_DEST[383:352] (cid:197) (TMP_SRC[383:256] &gt;&gt; (ORDER[7:6] * 32))[31:0];
    TMP_DEST[415:384] (cid:197) (TMP_SRC[511:384] &gt;&gt; (ORDER[1:0] * 32))[31:0];
    TMP_DEST[447:416] (cid:197) (TMP_SRC[511:384] &gt;&gt; (ORDER[3:2] * 32))[31:0];
    TMP_DEST[479:448] (cid:197)(TMP_SRC[511:384] &gt;&gt; (ORDER[5:4] * 32))[31:0];
    TMP_DEST[511:480] (cid:197) (TMP_SRC[511:384] &gt;&gt; (ORDER[7:6] * 32))[31:0];
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*
                                                              ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );</p>
<p>VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );</p>
<p>VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );</p>
<p>VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );</p>
<p>VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );</p>
<p>VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );</p>
<p>VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );</p>
<p>(V)PSHUFD:__m128i _mm_shuffle_epi32(__m128i a, int n)</p>
<p>VPSHUFD:__m256i _mm256_shuffle_epi32(__m256i a, const int n)</p>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E4NF.</td></tr>
<tr>
<td>If VEX.vvvv ≠ 1111B or EVEX.vvvv ≠ 1111B.</td></tr></table></body></html>